Method for connecting test bench elements and shell device

ABSTRACT

Method for connecting test bench elements and shell device The invention provides a method for connecting test bench elements ( 102   a - 102   f ), and a shell device, a test bench element shell ( 201 ) partially or completely surrounding a circuit unit ( 101 ) to be verified, so that test bench elements ( 102   a - 102   f ) can be connected to the test bench element shell ( 201 ). Test data streams ( 203   a - 203   f ) pass in each case between the test bench elements ( 102   a - 102   f ) and the test bench element shell ( 201 ), the test bench element shell ( 201 ) which surrounds the circuit unit ( 101 ) to be verified being connected via interface data streams (P 0 ( 0 )-P 0 ( 7 ), P 1 ( 0 )-P 1 ( 7 ),  204   a,    204   b,    204   c ) to the circuit unit ( 101 ) to be verified. The test bench element shell ( 201 ) ensures that in each case a specific protocol with associated operations can be executed, during which process, depending on the configuration, an interface exchanges interface data streams (P 0 ( 0 )-P 0 ( 7 ), P 1 ( 0 )-P 1 ( 7 ),  204   a - 204   c ) of the circuit unit ( 101 ) to be verified with the corresponding test bench element ( 102   a - 102   f ).

[0001] The present invention relates to a method for carrying out testsand simulations in order to check the functional correctness of acircuit unit, and relates in particular to a method for connecting testbench elements and to a shell device for carrying out the method.

[0002] Test benches are, for example, models which simulate theenvironment of a circuit design and corresponding input signals, andcheck output signals, for example signal responses, which are dependenton these input signals.

[0003] Such models are implemented, for example, but not exclusively, inhardware description languages such as VERILOG and VHDL. In many cases,it is possible to carry out a co-simulation of hardware units andsoftware units, such as is described, for example, in “Matthias Bauer,Wolfgang Ecker: Hardware/Software co-Simulation in a VHDL-based TestBench Approach, DAC 97, Anaheim, Calif., U.S.A.”.

[0004] In a test bench, for example, a model of a circuit arrangement orof a circuit design is simulated, it being necessary in many cases totake into account not only a functionality of the circuit design butalso a timing characteristic.

[0005] Test benches according to the prior art are, for example,constructed in such a way that one or more test bench elements areprovided as logic interfaces between a test bench controller and acircuit unit to be verified. A test bench element may be embodied, forexample, as a transactor or as a protocol generator, the respective testbench element generating the signal value profiles which are requiredfor a logic interface. A logic operation carried out on the signals anda definition of the respective signal value profiles correspond to aprotocol, specific sequences of signal value profiles being combined toform protocol operations, for example the operations:

[0006] “read memory”;

[0007] “send ATM (asynchronous transfer mode) cell”;

[0008] etc.

[0009] and such protocol operations can in turn be interleaved with oneanother in order to carry out, for example, the following operations:

[0010] “carry out DMA transmission”;

[0011] “send ATM cell sequence” in order to reprogram ATM switch,

[0012] etc.

[0013] Such protocol-operation-related description facilitates aconfiguration of test bench elements which can be in turn repeatedlyre-used when tests are carried out.

[0014] If a plurality of protocol-generating units share one interfacewhich can then itself only be used alternately, or if a programmableprotocol generator which can generate different protocols is located onthe circuit unit to be verified, it is disadvantageously impossible todirectly use or connect a test bench element which generates only oneprotocol.

[0015] In order to be able to connect through specific interfaces and/orspecific interface signals or interface data streams to correspondingtest bench elements, different types of interfaces or interface signalsmust be taken into account, for example:

[0016] serial interfaces,

[0017] parallel interfaces, and

[0018] individual bits or groups of bits which are to be set and/or tobe read.

[0019] The circuit unit to be verified can be formed by any desiredcircuit unit, for example a microprocessor, a microchip graphics card,etc., digital signals, if appropriate however also analog and digitalsignals, being predominantly processed.

[0020] Test bench elements are appropriately configured in such a waythat they can be used with the largest possible number of circuit unitsto be verified, under the largest possible number of test and simulationconditions. A test bench controller is conventionally used as a centralcontrol element which makes it possible to control the entire course ofa test and/or of a simulation. A test or simulation program which isprovided in a centralized or decentralized fashion is conventionallyapplied to the test bench controller.

[0021] Furthermore, the test bench controller communicates with eachindividual test bench element by means of a control data stream, aconnection being provided between the test bench controller and therespective test bench element. A sequence of protocol operations may bespecified, for example, in a test bench element, said operations beingeither permanently coded in a model or a desired sequence of protocoloperations being read from a file.

[0022] In some cases, the test bench elements can be synchronized withone another. Here, when intersecting tests are simulated, during whichall the protocol operations of all the test bench elements are to becarried out, protocol operations which occur simultaneously at differentpoints, i.e. in a respective test bench element, must be specified.

[0023] Conventional test and simulation methods therefore predominantlyuse test bench architectures which are controlled by a test benchcontroller as the central unit, individual test bench elements beinginformed as to which protocol operations are to be carried out.Furthermore, it is necessary to ensure that the test bench elements caninform the test bench controller about the degree of success and thedata with which a sequence of the specific protocol operations wascarried out or terminated.

[0024]FIG. 4 shows a conventional method for simulating and testing acircuit unit 101 to be verified, by means of a simulation program storedin a control element 104. As is shown in FIG. 4, the control element 104which contains a specific simulation program is connected to the testbench controller 103, a controller data stream 114 being transferred tothe test bench controller 103 by the control element 104.

[0025] Test bench elements 102 a-102 n are conventionally connected bymeans of control data streams 111 a-111 n.

[0026] It is to be noted that one or more test bench elements 102 a, . .. 102 i, . . . 102 n may be present, i representing an index.

[0027] For example, FIG. 4 illustrates five different test benchelements, the test bench element 102 a corresponding, for example, to aserial interface which exchanges data with the circuit unit 101 to beverified, by means of a serial test data stream 112. As a furtherexample, the test bench 102 n is illustrated as a parallel interfacewhich exchanges test data with the circuit unit 101 to be verified, bymeans of a parallel test data stream 113.

[0028] In the same way, data is exchanged between the other test benchelements and the circuit unit 101 to be verified, specified data streams(not shown) being exchanged. For example, FIG. 4 illustrates five testbench elements 102 a, 102 b, 102 i, 102 i+1 and 102 n, but it ispossible to provide fewer or more test bench elements. It is clearlyapparent that the number of control data streams 111 a, . . . 111 i,(i=index), . . . 111 n must correspond to the number of test benchelements 102 a-102 n.

[0029] This conventional connection of test bench elements 102 a-102 nto a central test bench controller 103 as central control element has aseries of disadvantages.

[0030] A main disadvantage of a conventional method for connecting testbench elements 102 a-102 n to the test bench controller 103 is that atest bench element that generates only one protocol cannot be used orconnected directly if a plurality of protocol-generating units share oneinterface which then itself can only be used alternately, or if aprogrammable protocol generator, which can generate different protocols,is present on the circuit unit to be verified.

[0031] A conventional stimulus generation is carried out at a bit leveland not at a protocol level, which permits different protocols to becreated but has the disadvantage that a transaction-based description ofthe interface protocols cannot be provided.

[0032] A further disadvantage of conventional methods for connectingtest bench elements is that an effective support of a connection of testbench elements which is directed at re-use cannot be provided.

[0033] Yet a further disadvantage of conventional methods for connectingtest bench elements is that a separate environment has to be generatedfor each configuration of an interface as a separate test and simulationdevice is necessary for each possible embodiment of an interface,precisely one embodiment of the interface having to be functionallychecked in each of these test/simulation devices by connecting acorresponding test bench element directly to the circuit element to beverified.

[0034] In addition, in methods for connecting test bench elementsaccording to the prior art, it is disadvantageously necessary to checkeach configuration of an interface by means of a specific simulation,which constitutes extremely disadvantageous properties in particularwhen hardware accelerators are used and when there is a simulation ofinterfaces and/or of interface signals or interface data streams whichcan change their specific configuration or their profile, for example bymeans of dynamically switchable pins, during operation.

[0035] Furthermore, different test bench elements may communicatesimultaneously with the circuit element to be verified, i.e. in the sametime interval, although this is not provided for in the test sequenceand/or simulation sequence. Here, there is a problem that a functionallyperfectly correctly functioning and functionally capable circuit elementcan exhibit faulty behavior which can advantageously only be interpretedwith difficulty, and can therefore usually only be eliminated with alarge degree of effort.

[0036] Furthermore, information which is present inter alia in the datastreams to be transmitted can disadvantageously be lost as a result ofthis multiple communication between different test bench elements andthe circuit unit to be verified. Here, it is, under certaincircumstances, possible in an inexpedient way for the circuit to carryon operating without faults or without issuing a fault message althoughit ought to terminate the execution or ought to issue a message.

[0037] Furthermore, it is inexpedient for the circuit logic to go intoundefined, unreproducible states. A disadvantage is especially thatthese states can no longer be eliminated in many cases.

[0038] Furthermore, with conventional methods it is problematic thatdifferent test bench elements access one interface. Here, it isdisadvantageously possible for driver conflicts to occur if a test benchelement inadmissibly attempts to access the circuit unit to be verified.

[0039] It is thus an object of the present invention to provide a methodfor connecting test bench elements which permits a plurality ofprotocol-generating units to divide one interface, different types ofinterfaces being taken into account, and a supervisory operation of astate being provided; and/or a control operation of at least one testbench element being provided; and/or a means of monitoring, controllingand/or supervising a communication of at least one test bench elementwith the circuit unit to be verified being provided; and/or a means ofmodifying, diverting, assigning, controlling and/or monitoring aconnection structure of interface signals or buses and/or input/outputsignals or buses by means of test bench element shells being provided.

[0040] This object is achieved by means of a method for connecting testbench elements as claimed in claim 1 and a shell device having thefeatures of claim 41.

[0041] Further refinements of the invention emerge from the subclaims.

[0042] The core of the invention is a method for connecting test benchelements, a circuit unit to be verified being introduced into atest/simulation device, being connected to at least one test benchelement shell in order to transfer interface data streams, the at leastone test bench element shell being connected to test bench elements inorder to transfer test data streams so that a through-connection ofinterface data streams to corresponding test bench elements is madepossible.

[0043] An essential idea of the invention also consists in the fact thata control operation and/or a monitoring operation of states and modes ofoperation of test bench elements is provided by means of at least onetest bench element supervisory shell, a means of monitoring, controllingand/or supervising a communication of at least one test bench elementwith the circuit unit to be verified also being provided, and a [sic]and/or a means for modifying, diverting, assigning, controlling and/ormonitoring a connection structure of interface signals or buses and/orinput/output signals or buses by means of the at least one test benchelement connection shell being provided.

[0044] The method according to the invention for connecting test benchelements as claimed in claim 1 and the shell device having the featuresof claim 31 have the following advantages.

[0045] An essential advantage of the method according to the inventionfor connecting test bench elements is that a test bench element whichgenerates only one protocol can be connected even if a plurality ofprotocol-generating units share one interface.

[0046] It is advantageously possible for a test bench element whichgenerates only one protocol to be connected even if a programmableprotocol generator with which different protocols can be generated islocated on the circuit unit to be verified.

[0047] A further advantage of the method according to the invention forconnecting test bench elements is that interfaces of a circuit unit tobe verified can be configured on the basis of signal values at specificconnection elements of the circuit unit to be verified, a specificsignal value deciding, for example, whether an interface is operated inan X mode or a Y mode.

[0048] The method according to the invention for connecting test benchelements can advantageously monitor a correct method of operation oftest bench elements and a communication of test bench elements.

[0049] In addition, an advantage of the method according to theinvention is that a connection structure of interface signals or busesand/or input/output signals or buses can be modified in a predefinableway during a simulation or during a test of the circuit unit to beverified. Here, in particular interface signals or buses and/orinput/output signals or buses can be connected, diverted or assigned toone another on a temporary or even long-term basis.

[0050] The method according to the invention for simulating and fortesting a circuit unit to be verified in which interfaces of the circuitunit to be verified can be connected to different test bench elements ofa test/simulation device have essentially the following steps:

[0051] a) the circuit unit to be verified is connected to at least onetest bench element shell of the test/simulation device in order totransfer and switch interface data streams which are correspondinglyoutput to the associated test bench elements by the circuit unit to beverified;

[0052] b) the at least one test bench element shell is connected to thetest bench elements in order to transfer test data streams which areoutput by the test bench elements to the circuit unit to be verified;

[0053] c) at least one test bench element shell is controlled by meansof a shell control data stream which is provided by a test benchcontroller; and

[0054] d) the interface data streams are evaluated by a test benchelement shell which is connected to the test bench elements, in order tocheck the operational capability of the circuit unit to be verified.

[0055] In the subclaims there are advantageous developments andimprovements of the respective subject matter of the invention.

[0056] According to one preferred development of the present invention,a test bench element shell is placed completely around a circuit unit tobe verified in order to provide a through-connection of interface datastreams to corresponding test bench elements.

[0057] According to a further preferred development of the methodaccording to the invention, a test bench element shell is partiallyplaced around a circuit unit to be verified in order to provide apartial through-connection of interface data streams to correspondingtest bench elements.

[0058] According to yet a further preferred development of the presentinvention, a test bench element shell is divided into at least two testbench element shell components so that interface data streams can beapplied to different embodiments of test bench elements.

[0059] According to yet a further preferred development of the presentinvention, the at least one test bench element shell or the at least onetest bench element shell component is provided as a test bench elementsupervisory shell for supervising, monitoring and analyzing data streamsbetween test bench elements and the circuit unit to be verified.

[0060] According to yet a further preferred development of the presentinvention, the at least one test bench element shell or the at least onetest bench element shell component is provided as a test bench elementconnection shell for modifying, diverting, assigning, controlling and/ormonitoring a connection structure.

[0061] According to yet a further preferred development of the presentinvention, a configuration which connects interface data streams of thecircuit unit to be verified to a corresponding test bench element isprovided in a test bench element shell component.

[0062] According to yet a further preferred development of the presentinvention, connections of test bench elements to the circuit unit to beverified are formed at the start of or during a simulation and/or a testand then remain fixed.

[0063] According to yet a further preferred development of the presentinvention, connections of test bench elements to the circuit unit to beverified are modified during a simulation/test.

[0064] According to yet a further preferred development of the presentinvention, a test bench element shell and/or a test bench element shellcomponent and/or a test bench element supervisory shell and/or a testbench element connection shell are configured by means of a central testbench controller.

[0065] According to yet a further preferred development of the presentinvention, a test bench element shell and/or a test bench elementcomponent shell and/or a test bench element supervisory shell and/or atest bench element connection shell are configured independently bymeans of table/data structures or files.

[0066] According to yet a further preferred development of the presentinvention, a capacity to re-use and structure test benches using testbench element shells is increased by virtue of the fact that test benchelements are not structurally connected to a test bench element shell orat least two test bench element shells at the highest level but ratherare also connected in a separate subunit, at least one test benchelement being integrated into a test bench element shell or a test benchelement shell component.

[0067] According to yet a further preferred development of the presentinvention, interfaces of a circuit unit to be verified are configured bymeans of signal values at specific connection elements of the circuitunit to be verified, in which case, for example, a specific signal valueand a connection element of the circuit unit to be verified deciding,during a reset phase, whether an interface is operated in an X mode or aY mode.

[0068] According to yet a further preferred development of the presentinvention, the test bench element shell and/or the at least one testbench element shell component are provided in order to set and/oranalyze signal values which are provided in order to configureinterfaces of the circuit unit to be verified.

[0069] According to yet a further preferred development of the presentinvention, a plurality of signals or all the signals which pass througha test bench element shell and/or at least one test bench element shellcomponent are logged, storage being provided in a file, a data structureand/or a table.

[0070] According to yet a further preferred development of the presentinvention, the test bench element shell and/or the at least one testbench element shell component are formed as a data multiplexer in orderto demultiplex multiplexed signals.

[0071] According to yet a further preferred development of the presentinvention, the test bench element shell and/or the at least one testbench element shell component are actuated by a test bench controller.

[0072] According to yet a further preferred development of the presentinvention, the test bench element shell and/or the at least one testbench element shell component are actuated by means of at least one testbench element.

[0073] According to yet another preferred development of the presentinvention, a structural composition of log-generating test benchelements is provided, an instantiation of test bench elements being madepossible at a lower level within a test bench element shell.

[0074] According to yet a further preferred development of the presentinvention, configuration signals are applied to the circuit unit to beverified in order to configure connection elements.

[0075] According to yet a further preferred development of the presentinvention, configuration signals are applied to the circuit unit to beverified in order to configure the at least one test bench element shellor the at least one test bench element shell component or the test benchelement supervisory shell or the test bench element connection shell.

[0076] According to yet a further preferred development of the presentinvention, configuration signals are applied to the at least one testbench element shell or test bench element shell component or test benchelement supervisory shell or test bench element connection shell inorder to configure it in a predefinable fashion.

[0077] According to yet a further preferred development of the presentinvention, a shell device is provided in order to generatetransaction-based vectors in a way which is compatible with fabricationtests.

[0078] According to yet a further preferred development of the presentinvention, a shell device is provided with which individual bits orgroups of bits are set, reset or read.

[0079] According to yet a further preferred development of the presentinvention, a shell device is provided with which not only structuralhierarchies but advantageously also logical hierarchies such as forexample a class hierarchy, a call hierarchy, etc. are provided.

[0080] According to yet a further preferred development of the presentinvention, a shell device is provided in the form of at least one testbench element supervisory shell which can both create or write andevaluate or analyze data streams.

[0081] According to yet a further preferred development of the presentinvention, a shell device or at least one test bench element supervisoryshell is provided which either permits test bench elements both tocreate or write and evaluate or analyze data streams, or rules out thelatter in a predefinable fashion.

[0082] According to yet a further preferred development of the presentinvention, an analysis and/or an evaluation of data streams within theat least one test bench element supervisory shell is provided by meansof evaluation units which are constructed on an interface-specificbasis. These evaluation units can therefore be advantageouslyimplemented in a variable fashion, and thus re-used, for a correspondinginterface in any desired different test bench supervisory shells.

[0083] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided in such a way that a simultaneous accessby test data streams of different test bench elements to a singleinterface data stream is prevented.

[0084] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided in such a way that a simultaneous accessby test data streams of different test bench elements to one interfacedata stream in each case is prevented.

[0085] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided in such a way that a simultaneous accessof test data streams of any desired number of test bench elements to anydesired number of interface streams is prevented.

[0086] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided in such a way that a simultaneoustransmission of instruction sequences of different test bench elementsis prevented.

[0087] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided in such a way that in each case a timewindow is assigned to the at least one test bench element.

[0088] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell is provided by analyzing or by detecting transmitteddata streams in the test bench element supervisory shell itself.

[0089] According to yet a further preferred development of the presentinvention, a control operation of at least one test bench elementsupervisory shell by means of a shell control data stream and/or byanalyzing or by detecting transmitted data streams prevent thetransmission of specific instruction sequences and/or data sequences bythe at least one test bench element to the circuit unit to be verified.

[0090] According to yet a further preferred development of the presentinvention, a monitoring operation of test data streams, transmitted viathe at least one test bench element supervisory shell, by means of ashell control data stream and/or by analyzing or by detectingtransmitted data streams is provided in such a way that a warningmessage is issued when there is an unauthorized transmission by the atleast one test bench element.

[0091] According to yet a further preferred development of the presentinvention, a monitoring process of test data streams, transmitted viathe at least one test bench element supervisory shell, by means of ashell control data stream and/or by analyzing or by detectingtransmitted data streams is provided in such a way that a prioritizationof, for example, both the accessing test bench elements and the datasequences and/or instruction sequences to be transmitted or the datastreams and/or instruction streams is carried out.

[0092] According to yet a further preferred development of the presentinvention, a control operation and/or a monitoring operation of testdata streams, transmitted via the at least one test bench elementsupervisory shell, by means of a shell control data stream and/or byanalyzing or by detecting transmitted data streams is provided for anydesired predefinable number of test bench elements connected to the atleast one test bench element supervisory shell.

[0093] The shell device according to the invention for connecting testbench elements also has:

[0094] a) a circuit unit to be verified in a test/simulation device;

[0095] b) at least one test bench element; and

[0096] c) at least one test bench element shell for connecting thecircuit unit to be verified to the at least one test bench element inorder to transfer and switch interface data streams and test datastreams.

[0097] Exemplary embodiments of the invention are illustrated in thedrawings and explained in more detail in the following description.

[0098] In the drawings:

[0099]FIG. 1 shows a test bench element shell, arranged between acircuit unit to be verified and corresponding test bench elements,according to a preferred embodiment of the present invention;

[0100]FIG. 2 shows a test bench element shell which partially surroundsa circuit unit to be verified, according to a further preferredembodiment of the present invention;

[0101]FIG. 3 shows a test bench element shell, divided into a first testbench element shell component and a second test bench element shellcomponent, according to a further exemplary embodiment of the presentinvention;

[0102]FIG. 4 shows a conventional method for connecting test benchelements to a circuit unit to be verified;

[0103]FIG. 5 shows two test bench element supervisory shells, arrangedbetween the circuit unit to be verified and corresponding test benchelements, according to a further preferred embodiment of the presentinvention; and

[0104]FIG. 6 shows a test bench element connection shell, arrangedbetween the circuit unit to be verified and corresponding test benchelements, according to a further preferred embodiment of the presentinvention.

[0105]FIG. 1 shows a test bench element shell, arranged between acircuit unit to be verified and corresponding test bench elements, inaccordance with an embodiment of the present invention.

[0106] In the arrangement shown in FIG. 1, three test bench elements 102a, 102 b and 102 c are shown by way of example, the test bench elements102 a and 102 b having serial interfaces in order to exchange serialtest data streams 112 via a test bench element shell 201 with thecircuit unit 101 to be verified, and the test bench element 102 c beingprovided with a parallel interface in order to exchange a parallel testdata stream 113 via the test bench element shell 201 with the circuitunit 101 to be verified.

[0107] However, it is to be noted that more than three or less thanthree test bench elements can be connected to the test bench elementshell 201. In the exemplary embodiment shown in FIG. 1, the test benchelement shell 201 is in turn connected via interface data streamsP0(0)-P0(7) to a circuit unit 101 to be verified, a total of eight linesfor exchanging data streams between interfaces being provided here.Further interface data streams 202 can in principle be exchanged withthe circuit unit 101 to be verified. Each individual test bench element102 a-102 c contains specific control data streams 111 a-111 c from atest bench controller 103.

[0108] Furthermore, as indicated by a dashed line 111 d, a control datastream is routed directly from the test bench controller 103 to the testbench element shell 201 in order to permit specific configurations ofinterfaces to be defined. Further control data streams, as indicated bya dashed arrow 111 i (i=index), show that more than three test benchelements 102 a-102 c can be actuated by the test bench controller 103.For the sake of clarity and in order to avoid an overlappingdescription, the test bench controller 103 and connections between thetest bench controller 103 and corresponding test bench elements 102a-102 g are omitted in the following FIGS. 2 and 3, only control datastreams 111 a-111 g being indicated in the form of double arrows inFIGS. 2 and 3.

[0109] The test bench element shell 201 shown in FIG. 1 will beexplained below in more detail with reference to FIGS. 2 and 3.

[0110]FIG. 2 shows a test bench element shell which partially surroundsa circuit unit to be verified, according to an embodiment of the presentinvention.

[0111] In the arrangement shown in FIG. 2, a test bench element shell201 almost completely surrounds a circuit unit 101 to be verified sothat the test bench elements 102 a-102 f can be connected to the testbench element shell 201. Only a seventh test bench element 102 g isdirectly connected via a test data stream 203 g to the circuit unit 101to be verified.

[0112] It is to be noted that in the exemplary embodiment shown in FIG.2 six test bench elements 102 a-102 f are connected directly to the testbench element shell 201, while one test bench element 102 g is connecteddirectly to the circuit unit 101 to be verified, but that a differentnumber from the number of test bench elements shown in FIG. 2 can beconnected directly to the circuit unit 101 to be verified or the testbench element shell 201. Test data steams 203 a-203 f each pass betweenthe test bench elements 102 a-102 f and the test bench element shell201. A test data stream 203 g passes between a test bench element 102 gand the circuit unit 101 to be verified.

[0113] While the test bench element 102 g is connected according to theprior art shown in FIG. 4, the test bench elements 102 a-102 f in FIG. 2are connected via the test bench element shell 201 according to anexemplary embodiment of the present invention. The test bench elementshell 201 which surrounds a circuit unit 101 to be verified is in turnconnected via interface data streams 204 a, 204 b and 204 c to thecircuit unit 101 to be verified. In the exemplary embodiment of themethod according to the invention for connecting test bench elements,which is shown in FIG. 2, the test bench element shell 201 then ensuresthat in each case a specific protocol can be executed with associatedoperations, in which case, depending on the configuration, an interfaceconnects interface data streams of the circuit unit to be verified tothe corresponding test bench element. Connections of test bench elementsto the circuit unit 101 to be verified can be established at the startof a simulation or of a test and then remain fixed, but they can also bemodified during a simulation or a test.

[0114] A test bench element shell 201 can thus be configured by means ofa central test bench controller 103 or in a decentralized way by meansof further test bench elements 102 a-102 g or completely independentlyby means of externally predefinable tables, data structures or files.

[0115]FIG. 3 illustrates a test bench element shell, divided into afirst test bench element shell component 301 and a second test benchelement shell component 302, in accordance with a further exemplaryembodiment of the present invention.

[0116] The exemplary embodiment of the present invention shown in FIG. 3has a modified test bench element shell, the test bench element shellbeing split into a first test bench element shell component 301 and asecond test bench element shell component 302. It is to be noted thatthe test bench element shell can also be split into more than two testbench element shell components. As shown in FIG. 3, the four test benchelements 102 a-102 d are connected via the first test bench elementshell component 301 to the circuit unit 101 to be verified, while thetest bench elements 102 e and 102 f are integrated into the second testbench element shell component 302. The seventh test bench element 102 gis, as shown in FIG. 2, conventionally connected by means of a test datastream 203 g directly to the circuit unit 101 to be verified.

[0117] The other connections shown in FIG. 3 correspond to theconnections shown in FIG. 2, which are not described here again in orderto avoid an overlapping description.

[0118] In the arrangement shown in FIG. 3, the test bench elements 102 eand 102 f are not connected structurally at the highest level but ratherconnected structurally in a separate test bench element shell component302 in order to improve a capacity to re-use and structure test bencheswith the test bench element shell concept. The test bench elements 102 eand 102 f in the exemplary embodiment of the present invention can thusbe instantiated in a separate test bench element shell component 302 ata low level.

[0119]FIG. 5 shows two test bench element supervisory shells, i.e. afirst test bench element supervisory shell 401 and a second test benchelement supervisory shell 402, which are arranged between the circuitunit 101 to be verified and corresponding test bench elements 102 a-102n.

[0120] The block diagram shown in FIG. 5 illustrates an arrangementaccording to a preferred exemplary embodiment of the present invention.The circuit unit 101 to be verified is connected via first interfacedata streams P0(0)-P0(3) to the first test bench element supervisoryshell 401 which exchanges serial test data streams 112 with the testbench elements 102 a, 102 b, and via second interface data streamsP1(0)-P1(7) to a second test bench element supervisory shell 402 whichexchanges parallel test data streams 113 to the test bench elements 102i and 102 n.

[0121] It is to be noted that in principle more than two test benchelements supervisory shells 401, 402 can be connected. According to theexemplary embodiment of the present invention in FIG. 5, the test benchelement supervisory shells 401 and 402 have specific features whichpermit signals to be supervised or monitored and controlledunidirectionally and bidirectionally.

[0122] Furthermore, FIG. 5 illustrates that the second test benchsupervisory shell 402 receives a shell control data stream 403 from thetest bench controller 103, while the first test bench supervisory shell401 responds to transferred signal profiles or data streamsindependently of the test bench controller 103.

[0123] Supervision or monitoring or controlling of a state of test benchelements 102 a-102 n or of modes of operation of the test bench elements102 a-102 n then leads according to the invention to differentconsequences.

[0124] Firstly, the test bench element supervisory shell 401 issues awarning message or a fault message if a plurality of different testbench elements 102 a-102 n simultaneously access one interface in eachcase and/or a single interface in total or if specific, unauthorizedsuccessions of signal sequences or instruction sequences occur.

[0125] Secondly, at least one test bench element supervisory shell 401or 402 can carry out a predefinable prioritization which permits thecorresponding interface to be accessed by the test bench elements 102a-102 n in a predefinable sequence, or permits a conflict to be avoidedwhen there is simultaneous access.

[0126] Finally, the test bench element supervisory shells 401, 402 canblock one or more instruction sequences in the transmitted data streamsso that only authorized instruction sequences can be transmitted.

[0127]FIG. 6 illustrates a test bench element connection shell 601,arranged between the circuit unit 101 to be verified and correspondingtest bench elements 102 a-102 n, according to a further preferredembodiment of the present invention.

[0128] The circuit unit 101 to be verified is connected via firstinterface data streams P0(0)-P0(3) and via second interface data streamsPl(0)-Pl(7) to the test bench element connection shell 601, serial testdata streams 112 being exchanged with the test bench elements 102 a, 102b in this example, and parallel test data streams 113 being exchangedwith the test bench elements 102 i and 102 n.

[0129] Furthermore, FIG. 6 illustrates that the test bench elementconnection shell 601 receives a shell control data stream 403 from thetest bench controller 103.

[0130] Furthermore, test bench element connection shell 601 responds totransferred signal profiles or data streams independently of the testbench controller 103.

[0131] In order to avoid a description which overlaps with FIG. 5, moredetails will be given below on the specific properties of the test benchelement connection shell 601 in FIG. 6.

[0132] The test bench element connection shell 601 is used in particularto form an interface connection 602 (shown by way of example in FIG. 6)between interface signals or buses and/or input/output signals or busesof the circuit unit 101 to be verified. Furthermore, different interfaceconnections 602 may be present simultaneously and form any desiredconnection structures between the corresponding interfaces.

[0133] It is to be noted that all of the embodiments of a test benchelement shell which are given above (for example a test bench elementsupervisory shell, a test bench element connection shell, etc.) as wellas their modes of operation can be combined, interleaved, joined and/orintegrated in any desired fashion. For example, a test bench elementconnection shell can thus both analyze the data streams and modify theconnection structure as well as monitoring the communication of a testbench element. Any different combinations can be implemented and can beprovided in accordance with the respective requirements.

[0134] Reference is made to the introduction to the description withrespect to the conventional method illustrated in FIG. 4 for connectingtest bench elements to a circuit unit to be verified.

[0135] Although the present invention has been described above by meansof preferred exemplary embodiments, it is not restricted to them butrather can be modified in various ways.

[0136] LIST OF REFERENCES

[0137] In the figures, identical references designate identical orfunctional identical components.

[0138]101 Circuit unit to be verified

[0139]102 a, 102 i, . . . 102 n, Test bench elements (i=index)

[0140]103 Test bench controller

[0141]104 Controller

[0142]111 a, . . . 111 i, . . . 111 n Control data stream (i=index)

[0143]112 Serial test data stream

[0144]113 Parallel test data stream

[0145]114 Controller data stream

[0146]201 Test bench element shell

[0147]202 Further interface data streams

[0148]203 a, . . . , 203 g Test data streams

[0149]204 a, 204 b 204 c Interface data streams

[0150]301 First test bench element shell component

[0151]302 Second test bench element shell component

[0152] P0(0), . . . , P0(7), P0(0), . . . , P0(3) P1(0), . . . , P1(7)Interface data streams

[0153]401 First test bench element supervisory shell

[0154]402 Second test bench element supervisory shell

[0155]403 Control data stream

[0156]601 Test bench element connection shell

[0157]602 Interface connection

1. A method for simulating and testing a circuit unit (101) to beverified, in which method interface data streams (P0(0)-P0(7),P1(0)-P1(7), 203 a-204 c) of the circuit unit (101) to be verified areexchanged with test bench elements (102 a-102 n) in a test/simulationdevice, having the steps: a) the circuit unit (101) to be verified isconnected to at least one test bench element shell (201, 301, 302, 401,402) of the test/simulation device in order to transfer and switchinterface data streams (204 a, 204 b, 204 c) which are correspondinglyoutput to the associated test bench elements (102 a-102 n) by thecircuit unit (101) to be verified; b) the at least one test benchelement shell (201, 301, 302, 401, 402) is connected to the test benchelements (102 a-102 n) in order to transfer test data streams (203 a-203n) which are output by the test elements (102 a-102 n) to the circuitunit (101) to be verified; c) at least one test bench element shell(401, 402) is controlled by means of a shell control data stream (403)which is provided by a test bench controller (103); and d) the interfacedata streams (P0(0)-P0(7), P1(0)-P1(7), 204 a, 204 b, 204 c) areevaluated by a test bench element shell which is connected to the testbench elements (102 a-102 n), in order to check the correct operationalcapability of the circuit unit (101) to be verified.
 2. The method asclaimed in claim 1, wherein a test bench element shell (201) is arrangedcompletely around a circuit unit (101) to be verified, in order toprovide a through-connection of interface data streams (204 a-204 c) tocorresponding test bench elements (102 a-102 n).
 3. The method asclaimed in one or both of claims 1 and 2, wherein a test bench elementshell (201) is arranged partially around a circuit unit (101) to beverified in order to provide a partial through-connection of interfacedata streams (204 a-204 c) to corresponding test bench elements (102a-102 n).
 4. The method as claimed in one or more of claims 1 to 3,wherein a test bench element shell (201) is divided into at least twotest bench element shell components (301, 302) so that interface datastreams (204 a-204 c) can be applied to different embodiments of testbench elements.
 5. The method as claimed in claims 1 and 4, wherein aconfiguration which connects interface data streams (204 a-204 c) of thecircuit unit (101) to be verified to a corresponding test bench element(102 a-102 n) is provided in a test bench element shell component (301,302).
 6. The method as claimed in one of more of claims 1 to 5, whereinconnections of test bench elements (102 a-102 n) to the circuit unit(101) to be verified are formed at the start of or during a simulationand/or a test and then remain fixed.
 7. The method as claimed in one ormore of claims 1 to 6, wherein connections of test bench elements (102a-102 n) to the circuit unit (101) to be verified are modified during asimulation and/or a test.
 8. The method according to one or more ofclaims 1 to 7, wherein a configuration of a test bench element shell(201, 301, 401, 402, 601) is provided by means of a central test benchcontroller (103).
 9. The method as claimed in one or more of claims 1 to8, wherein a configuration of a test bench element shell (201, 301, 302,401, 402, 601) is provided in a decentralized fashion by means of atleast one test bench element (102 a-102 n).
 10. The method as claimed inone or more of claims 1 to 9, wherein a capacity to re-use and structuretest benches using test bench element shells (201, 301, 302) isincreased by connecting test bench elements to a test bench elementshell (201) or at least two test bench element shell components (301,302) in a separate subunit, at least one test bench element beingintegrated into a test bench element shell (201) or a test bench elementshell component (301, 302).
 11. The method as claimed in one or more ofclaims 1 to 10, wherein interfaces of a circuit unit (101) to beverified are configured by means of signal values at specific connectionelements of the circuit unit (101) to be verified and the correspondingshell, a predefinable signal value at a connection element of thecircuit unit to be verified defining, during a reset phase, whether aninterface is operated in an X mode or Y mode.
 12. The method as claimedin one or more of claims 1 to 11, wherein the test bench element shell(201) and/or the at least one test bench element shell component (301,302) are provided in order to set and/or analyze signal values which areprovided in order to configure interfaces of the circuit unit (101) tobe verified.
 13. The method as claimed in one or more of claims 1 to 12,wherein a shell device with which individual bits are set, reset or readis provided.
 14. The method as claimed in one or more of claims 1 to 13,wherein a plurality of signals or all the signals which pass through atest bench element shell (201) and/or at least one test bench elementshell component (301, 302) are logged, storage of the logged signalsbeing provided in a file, a table and/or a data structure.
 15. Themethod as claimed in one or more of claims 1 to 14, wherein the testbench element shell (201) and/or the at least one test bench elementshell component (301, 302) are embodied as a data multiplexer in orderto demultiplex multiplexed signals.
 16. The method as claimed in one ormore of claims 1 to 15, wherein the test bench element shell (201)and/or the at least one test bench element shell component (301, 302)are actuated by a test bench controller (103) by means of a control datastream (111 d).
 17. The method as claimed in one or more of claims 1 to16, wherein a configuration of the test bench element shell (201) and/orof the at least one test bench element shell component (301, 302) isprovided by means of externally predefinable tables, data structuresand/or files.
 18. The method as claimed in one or more of claims 1 to17, wherein a structural composition of log-generating test benchelements (102 a-102 n) is provided, an instantiation of test benchelements (102 a-102 n) being provided on a lower level within a testbench element shell (201, 301, 302).
 19. The method as claimed in one ormore of claims 1 to 18, wherein configuration signals are applied to theat least one test bench element shell (201, 301, 302, 401, 402, 601) inorder to configure it in a predefinable fashion.
 20. The method asclaimed in one or more of claims 1 to 19, wherein configuration signalsare applied to the circuit unit (101) to be verified in order toconfigure a test bench element shell (201) and/or at least one testbench element shell component (301, 302).
 21. The method as claimed inone or more of claims 1 to 20, wherein at least one test bench elementshell (201, 301, 301, 401, 402, 601) is provided and is used to providestructural hierarchies and/or logic hierarchies, for example a classhierarchy, a call hierarchy, etc.
 22. The method as claimed in one ormore of claims 1 to 21, wherein at least one test bench element shell(201, 301, 302, 401, 402, 601) is provided in order to generatetransaction-based vectors in a way which is compatible with fabricationtests.
 23. The method as claimed in one or more of claims 1 to 22,wherein at least one test bench element shell (201, 301, 302, 401, 402,601) is provided, during which process test bench elements (102 a-102 n)are either allowed to create or write and evaluate or analyze datastreams, or are prevented from doing so.
 24. The method as claimed inclaim 1, wherein a control operation of at least one test bench elementsupervisory shell (401, 402) is provided in such a way that asimultaneous access by test data streams (112, 113) of different testbench elements (102 a-102 n) to a single interface in each case isprevented.
 25. The method as claimed in claim 1, wherein a controloperation of at least one test bench element supervisory shell (401,402) is provided in such a way that a simultaneous transmission ofinstruction sequences of different test bench elements (102 a-102 n) isprevented.
 26. The method as claimed in claim 1, wherein a controloperation of at least one test bench element supervisory shell (401,402) is provided in such a way that in each case a time window isassigned to the at least one test bench element (102 a-102 n).
 27. Themethod as claimed in claims 1 and 26, wherein a control operation of atleast one test bench element supervisory shell (401, 402) is provided byanalyzing or by detecting transmitted data streams in the test benchelement supervisory shell (401) itself.
 28. The method as claimed inclaims 1, 24 and 27, wherein a control operation of at least one testbench element supervisory shell (401, 402) by means of a shell controldata stream (403) and/or by analyzing or by detecting transmitted datastreams prevents specific predefinable instruction sequences and/or datasequences being transmitted by the at least one test bench element (102a-102 n) to the circuit unit (101) to be verified.
 29. The method asclaimed in claims 1 and 24 to 28, wherein a control operation of atleast one test bench element supervisory shell (401, 402) by means of ashell control data stream (403) and/or by analyzing or by detectingtransmitted data streams is provided in such a way that exclusivelypredefinable instruction sequences and/or data sequences are transmittedby the at least one test bench element (102 a-102 n) to the circuit unit(101) to be verified.
 30. The method as claimed in claims 1 and 24 to29, wherein a monitoring operation of test data streams (112, 113),transmitted via the at least one test bench element supervisory shell(401, 402), by means of a shell control data stream (403) and/or byanalyzing or by detecting transmitted data streams is provided in such away that a warning message is issued when there is an unauthorizedtransmission by the at least one test bench element (102 a-102 n). 31.The method as claimed in claims 1 and 24 to 30, wherein a monitoringoperation of test data streams (112, 113), transmitted via the at leastone test bench element supervisory shell (401, 402), by means of a shellcontrol data stream (403) and/or by analyzing or by detectingtransmitted data streams is provided in such a way that a prioritizationis carried out.
 32. The method as claimed in claims 1 and 24 to 31,wherein a control operation and/or a monitoring operation of test datastreams (112, 113), transmitted via the at least one test bench elementsupervisory shell (401, 402), by means of a shell control data stream(403) and/or by analyzing or by detecting transmitted data streams forany desired predefinable number of test bench elements (102 a-102 n)connected to the at least one test bench element supervisory shell (401,402) is provided.
 33. The method as claimed in one or more of claims 1to 32, wherein at least one test bench element shell (201, 301, 302,401, 402, 601) with which data streams can be both created or writtenand evaluated or analyzed is provided.
 34. The method as claimed inclaim 1, wherein at least one evaluation unit is provided in at leastone test bench element shell (201, 301, 302, 401, 402, 601) in a waywhich is interface-specific and can be re-used as desired, in order toanalyze and evaluate data streams.
 35. The method as claimed in claims 1and 24, wherein a control operation of at least one test bench elementsupervisory shell (401, 402) is provided in such a way that asimultaneous access by test data streams (112, 113) of a plurality oftest bench elements (102 a-102 n) to, in total, a single interface isprevented.
 36. The method as claimed in claims 1, 24 and 35, wherein acontrol operation of at least one test bench element supervisory shell(401, 402) is provided in such a way that a simultaneous access by testdata streams (112, 113) of any desired number of test bench elements(102 a-102 n) to any desired number of interfaces is prevented.
 37. Themethod as claimed in claim 1, wherein a test bench element connectionshell (601) which establishes predefinable connection structures asinterface connections (602) is provided in order to form a means ofconnecting and/or diverting and/or assigning interface signals or busesas well as input/output signals or buses of the circuit unit (101) to beverified.
 38. The method as claimed in one of claims 1 and 37, wherein atest bench element connection shell (601) is provided which establishespredefinable connection structures as interface connections (602)temporarily during a simulation or a test or permanently in order toform in a flexible way a means for connecting and/or diverting and/orassigning interface signals or buses and input/output signals or busesof the circuit unit (101) to be verified.
 39. The method as claimed inone or more of claims 1 to 19, wherein configuration signals are appliedto the circuit unit (101) to be verified, in order to configureconnection elements.
 40. The method as claimed in claim 1, wherein atleast one specific evaluation unit which can be re-used as desired,employed as frequently as desired and is integrated into the at leastone test bench element shell is provided on an interface-specific basisin order to analyze and evaluate the data streams.
 41. A shell devicefor simulating and testing a circuit unit (101) to be verified, having:a) a circuit unit (101) to be verified, in a test/simulation device; b)at least one test bench element (102 a-102 n); and c) at least one testbench element shell (201, 201, 302, 401, 402, 601) for connecting thecircuit unit (101) to be verified to the at least one test bench element(102 a-102 n) in order to transfer and switch interface data streams(P0(0)-P0(7), P1(0)-P1(7), 204 a, 204 b, 204 c) and test data streams(112, 113).
 42. The shell device as claimed in claim 41, wherein thetest bench element shell (201) is divided into at least two test benchelement shell components (301, 302).
 43. The shell device as claimed inclaim 41, wherein the test bench element shell (201) is divided into atleast two test bench element supervisory shells (401, 402).
 44. Theshell device as claimed in claim 41, wherein a device for creating orwriting and/or for evaluating or analyzing data streams is provided,said device being capable of being integrated into any desiredpredefinable test bench element shells.
 45. The shell device as claimedin claim 41, wherein the test bench element shell (201) is divided intoat least two test bench element connection shells.